The parity bit is used in error detection. Three different settings are used, which are ODD, EVEN, and NONE parity.

The number of bits in each transmitted or received serial character. Either 7 or 8 data bits can be specified.

The stop bits is used to detect where one character ends and another starts. Either 1 or 2 stop bits can be specified. When stop bits is specified then stop bits are generated or checked in the transmit or receive data respectively.

Specifies which interrupt is emerged when the character is received from serial port.

The interrupt vector is a global interrupt indicator which is designed at several multi-serial adapters (such as four serial card, eight serial card ... etc.) to check which serial port emerges interrupt. Since several serial ports are designed at one adapter and use the common IRQ, so that interrupt vector is useful to detect which port emerges interrupt. For example, suppose interrupt vector address of hardware adapter is set to 2C2H, the relationship between each port corresponds to the interrupt indicator is shown in the follows. If you specify this interrupt vector address, when interrupt is emerged, device driver may check address 2C2H to find which port emerges interrupt.

The standard COM1 and COM2 need not interrupt vector. We will list several famous multi-serial adapters in the appendix D.

The bit 0 (DTR) and bit 1 (RTS) are hardware handshaking. To let PCCOM in the normal mode, you must set the bit 0 and bit 1 to 1. The bit 4 provides a loopback feature for diagnostic testing of the serial port. In this case, you must set bit 4 to be 0. OUT1 and OUT2 are auxiliary user designed output which is used to enable/disable interrupt in most adapters, so that you must control OUT1
and OUT2 carefully to let your serial port emerges an interrupt. You may set OUT1=0 and OUT2=1 to enable interrupt of the most standard COM1 and COM2 adapter, however some adapters may not work in this case, you can ask OUT1 and OUT2 control from origin hardware manufacturer or trial and error to find one of four combination (0,0), (0,1), (1,0), (1,1). Appendix D will list OUT1 and OUT2 signal of our multi-serial family. Some 8250/16450 chip will generate OUT1 = 1 and OUT2 = 1 when internal loop is selected (bit 4 is set to 1), so that they will not emerge an interrupt when internal loop feature is test.

The active status is used to specify activation status of interrupt vector. Either active low or high can be set. If active low is specified, when the corresponding bit of interrupt vector is 0, means the corresponding port emerges an interrupt, otherwise if the bit is 1, means no interrupt is active.

XON/XOFF is software handshaking, which is used to prevent the lost of data while communication between two serial ports. Suppose we connect two computer named local computer and remote computer, if local computer is too busy to receive data from remote computer,  it send XOFF (S/CTRL whose code is 17) to remote computer to notice he is in busy mode. When remote computer receives XOFF, it will stop transmission until the local computer sends XON (Q/CTRL whose code is 19) to continue transmission. The same manner is activated at remote computer.

The DTR/DSR is hardware handshaking. Data Set Ready(DSR) indicates that the modem or data set is ready to establish communications link and transfer data with the serial interface. Data Terminal Ready(DTR) informs the modem or data set that the serial interface is ready to communication.

The RTS/CTS is hardware handshaking. Clear To Send(CTS) and Request To Send(RTS) can be used to establish communication protocol. RTS informs the modem or data set that the serial interface is ready to transmit data.

The modem status which provides Data Carrier Detected(DCD) to indicate the voltage level of the associate RS232 line.

Indicates that a telephone ring signal has been received by the modem or data set.

Indicates whether the received data input is held in the spacing state for longer than a full word transmission time, that is, the total time of start bit + data bits + parity bit + stop bits.

Indicates that the received data character does not have the correct even or odd parity.

Indicates that data in the receiver buffer register was not ready by the processor before the next characters was transferred into the receiver buffer register, thereby destroying the previous character.

Received Data Register full. If the flag always set, it means the RS232 port hang up because no interrupt generated when data arrive. Please restart your computer when error occurs.